1. Field
Example embodiments relate to a method of manufacturing a semiconductor device, for example, to a method of manufacturing a semiconductor device having a buried gate.
2. Description of the Related Art
Memory cells may be reduced or minimized as the integration density of semiconductor devices increases. Accordingly, continuing efforts are being made to obtain a desired or predetermined cell capacitance in a reduced or minimized memory cell and improve cell transistor characteristics. As such, reduced or minimized memory cells may further require smaller cell transistors. In response to such reduction or minimization, various methods of controlling an impurity density in a diffusion layer of cell transistors have been suggested to embody cell transistors that do no have any problems in terms of cell transistor characteristics. However, as a channel length of cell transistors is decreased, various thermal treatments performed when manufacturing semiconductor devices make the control of the depth of a diffusion layer of a transistor more difficult, so that an effective channel length as well as a threshold voltage decrease and may result in short channel effects and thereby, cause problems in operating the cell transistor.
As a method of solving the above-mentioned problems, a buried-gate type transistor has been suggested, in which a trench is formed in a surface of a substrate, and a gate of the buried-gate type transistor is formed within the trench. In the buried-gate type transistor, the gate is formed within the trench to lengthen a distance between a source and a drain. Therefore, an effective channel length may be increased, and thus, short channel effects may be decreased.
Conventionally, in order to fabricate the buried-gate type transistor, an isolation region that defines an active region may be formed in a semiconductor substrate. Then, trenches may be formed in the active region and the isolation region of the semiconductor substrate to form gate electrodes in the trenches. However, as the width of the gate electrode is decreased to embody a higher integrated memory cell, the width of the trench to be formed in the semiconductor device decreases. If a trench with a narrow width as above is formed, an internal width of the trench formed in the isolation region may be slightly greater than an internal width of the trench formed in the active region even when trenches of the same dimension are each formed in the active region and the isolation region as will be described in more detail. Hence, before burying a gate material into the trench, a natural oxide film within the trench may be removed using a conventional etchant. In this case, the materials each constituting the active regions and the isolation regions have different etch rates with respect to the etchant used for removing the natural oxide film. Conventionally, the isolation region that is composed of an oxide film may be slightly consumed by the conventional etchant that removes the natural oxide film. As the result, the internal width of the trench formed in the isolation region is greater than that of the trench formed in the active region. For example, when a polysilicon mask is used as an etch mask for forming the trench, a sidewall of the polysilicon mask may be oxidized as much as a desired or predetermined thickness when forming a gate oxide film within the trench. Therefore, an entrance width of the trench may be less than the internal width of the trench in the isolation region, so that voids may be formed within the trench in the isolation region when performing deposition for burying the gate material within the trench.
If the gate oxide film is grown along the surfaces of the voids once the voids are formed within the trench as above, the gate material buried within the trench may not be recessed as desired because the oxide films formed on the surfaces of the voids may act as an etch mask when etching-back the gate material buried within the trench for forming the buried gate.
In order to overcome the above-described problems, cleaning may be performed after etching-back the gate material buried within the trench. However, if a cleansing solution permeates into the voids, a problem of isotropic etching may occur to adversely increase a removal quantity of the gate material buried within the trench to be more than an intended quantity. In order to form a buried gate having more uniform electrical characteristics for each cell, it may be important to identically control the recess quantity of the gate material buried into the trench. Excessive recess of the gate material within the trench may result in a line break and an increased resistance of the gate. Also, a recess that is less than a desired quantity may cause a short circuit between a buried gate and a direct contact (DC) adjacent to the buried gate. Therefore, the above-mentioned factors may negatively affect the reliability of an obtained transistor.